Taiwan steps up chip R&D, homegrown design software
ποΈ The Taiwanese Cabinet plans to invest NT $300 billion (US$9.51 billion) through 2033 in next-generation chip design and advanced semiconductor processes.
π¬ Seven university semiconductor institutes will receive subsidies for equipment linked via a single service platform under the Taiwan Chip-based Industrial Innovation Program.
βοΈ Research institutes plan to establish an atomic-scale process verification line specifically for sub-1-nanometer semiconductor processes.
π TSMC has begun high-volume production using its 2-nanometer process in the fourth quarter of 2025, marking a milestone in advanced manufacturing.
π» The government aims to develop homegrown electronic design automation (EDA) tools to reduce reliance on international vendors for chip layout and verification.
βοΈ ITRI will build an intelligent EDA cloud platform to integrate industry-developed tools into a complete chip-design toolchain.
π An advanced semiconductor pilot line is being built for startups and SMEs to support low-volume, high-mix trial production needs.
π― The initiative targets emerging areas like advanced packaging where EDA tools are currently underdeveloped, creating new market opportunities.
π€ Universities will develop key EDA tools for advanced packaging while industry partners contribute to the broader toolchain ecosystem.
- Taiwan Semiconductor Manufacturing Co. (TSMC) has successfully begun high-volume production using its 2-nanometer process in the fourth quarter of 2025, demonstrating leadership in advanced semiconductor manufacturing.
- The government's NT $300 billion investment through 2033 will directly support TSMC's ecosystem by funding research infrastructure and next-generation chip design capabilities.
- ITRI's development of an intelligent EDA cloud platform and integration of industry tools will strengthen the local supply chain, reducing dependency on foreign EDA vendors for TSMC's design needs.
- The establishment of an atomic-scale process verification line for sub-1-nanometer processes provides critical infrastructure that supports TSMC's roadmap toward even more advanced nodes.
- The creation of a pilot line for low-volume, high-mix trial production offers a flexible testing environment that benefits TSMC's innovation and customer development cycles.